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選擇DC/DC轉(zhuǎn)換器的最佳開(kāi)關(guān)頻率

Direct current-to-direct current (DC/DC) converters with faster switching frequencies are becoming popular due to their ability to decrease the size of the output capacitor and inductor to save board space. On the other hand, the demands from the point-of-load (POL) power supply increase as processor core voltage drops below 1V, making lower voltages difficult to achieve at faster frequencies due to the lower duty cycle.


Many power IC suppliers are aggressively marketing faster DC/DC converters that claim to save space. A DC/DC converter switching at 1 or 2 MHz sounds like a great idea, but there is more to understand about the impact to the power supply system than size and efficiency. Several design examples will be shown revealing the benefits and obstacles when switching at faster frequencies.

 

Selecting an Application
Three different power supplies were designed and built to show the trade offs of high switching frequency. For all three designs, the input voltage is 5V, the output voltage is 1.8V, and the output current is 3A. These requirements are typical for powering a performance processor such as a DSP, ASIC or FPGA. To bound the filter design and performance expectations, the allowable ripple voltage is 20 mV, which is about one percent of the output voltage, and the peak-to-peak inductor current is chosen at 1A.

 

Independent designs at frequencies of 350, 700, and 1600 kHz will be compared to illustrate the benefits and obstacles. The TPS54317, a 1.6 MHz, low-voltage, 3 A synchronous-buck DC/DC converter with integrated MOSFETs was chosen as the regulator in each example. The TPS54317 from Texas Instruments features a programmable frequency, external compensation and is intended for high-density processor power point-of-load applications.

 

Selecting the Inductor and Capacitor
The inductors and capacitors are chosen according to the following simplified formulas:


Equation 1:
V = L x di/dt
Rearranging: L ≥ Vout x (1-D)/(ΔI x Fs)
where: ΔI = 1 A peak-to-peak; D = 1.8 V/5 V="0".36

 

Equation 2:
I = C x dv/dt
Rearranging: C ≥ 2 x ΔI/(8 x Fs x ΔV)
where: ΔV = 20 mV, I = 1 A peak-to-peak

 

Equation 2 assumes a capacitor is used that has negligible series resistance, which is true for ceramic capacitors. Ceramic capacitors were chosen for all three designs because of their low resistance and small size. The multiplier of two shown above in the rearranged Equation 2 accounts for capacitance drop associated with DC bias, since this effect is not accounted for in the datasheets of most ceramic capacitors.


The circuit in Figure 1 was used to evaluate the performance of each design on the bench.

 

 

Figure 1: TPS54317 Reference Schematic.

 

The components in the schematic that do not have values are the components that were modified in each design. The output filter consists of L1 and C2. The values of these components for all three designs are listed in Table 1, and were chosen based on the results from the equations above.

Table 1: Capacitor and inductor selections at 350kHz, 700kHz, and 1600 kHz.

 

Note that the DC resistance of each inductor decreased as the frequency increased. This is due to less copper length needed for fewer turns. The error amplifier compensation components were designed independently for each switching frequency. The calculations for selecting the compensation values are beyond the scope of this article.

 

Minimum on-time
Digital converters-to-digital converter integrated circuits (IC) are characterized with a limit on the minimum controllable on-time, which is the narrowest achievable pulse width of the pulse width modulation (PWM) circuit. In a buck converter, the percentage of time that the field effect transistor (FET) is on during a switching cycle is called the duty cycle, and is equal to the ratio of the output voltage to input voltage.

 

For the converter example above, the duty cycle is 0.36 (1.8V/5.0V) and the minimum on-time of the TPS54317 is 150ns (max) as shown in the datasheet. The limit for the controllable pulse width results in a minimum achievable duty cycle, which can be easily calculated as shown in Equation 3. Once the minimum duty cycle is known, the lowest achievable output voltage can be calculated, as shown in Equation 4 and Table 2. The lowest output voltage is also limited by the reference voltage of the converter, which is 0.9V for the TPS54317.

 

Equation 3:
Minimum duty cycle =
Minimum on-time x Switching frequency

 

Equation 4:
Minimum Vout =
Vin x Minimum duty cycle (bounded by TPS54317 Vref)

 


 Table 2: Minimum output voltage with 150 ns minimum on-time.

 

In this example, a 1.8V outputa 1.2V output) can be generated with a 1.6 MHz switching frequency. However, if the frequency is 3MHz, the lowest possible output voltage is limited to 2.3 V and the DC/DC converter will skip pulses. The alternative is to lower the input voltage or reduce the frequency. It is a good idea to check the DC/DC converter datasheet for a guaranteed minimum controllable on-time before selecting a switching frequency.

 

Pulse Skipping
Pulse skipping occurs when the DC/DC converter cannot extinguish the gate drive pulses fast enough to maintain the desired duty cycle. The power supply will try to regulate the output voltage, but the ripple voltage will increase due to the pulses being further apart. Due to the pulse skipping, the output ripple will exhibit sub-harmonic components, which may present noise issues. It is also possible that the current limit circuit will no longer work properly since the IC may not respond to a large current spike. In some cases, the control loop may be unstable since the controller is not performing properly. The minimum controllable on-time is an important attribute and it is wise to check the DC/DC converter’s specification in the datasheet to verify a frequency and minimum on-time combination.

 

Efficiency and Power Dissipation
The efficiency of a DC/DC converter is one of the most important attributes to consider when designing a power supply. Poor efficiency translates into higher power dissipation which has to be managed on the circuit board with heat sinks or additional copper on the printed circuit board. Power dissipation also places a higher demand on the power supply upstream. Power dissipation has several components shown below:


The loss components of interest from our three examples come from the FET driving loss, the FET switching loss and the inductor loss. The FET resistance and IC loss are consistent since the same IC is used in all three designs. Since ceramic capacitors were chosen in each example, the capacitor loss is negligible due to their low equivalent series resistance. To show the effects of high frequency switching, the efficiency of each example was measured and illustrated in Figure 2.

 


 Figure 2: Efficiency at 5 V input and 1.8 V output at various frequencies.

 The figure clearly shows that the efficiency is decreased as switching frequency is increased. To improve efficiency at any frequency, look for a DC/DC converter with a low Rds (on), gate charge, or quiescent current specification at full load, or search for capacitors and inductors with lower equivalent resistance.

 

Size


Table 3 shows the inductor and capacitor values with the pad area required on the printed circuit board. 
 

Table 3: Component size and total area requirements

 

The recommended pad area of a capacitor or inductor is slightly larger than the individual component itself, and the pad area dimension is accounted for in each of the three design examples. Then, the total area was derived by adding the area occupied by each component, which includes the pad sizes for the IC, the filter and all other small resistors and capacitors multiplied by a factor of two to account for component spacing. The total area savings from 350 kHz to 1600 kHz is significant and provides a 50 percent reduction in filter size and a 35 percent reduction in board space, saving almost 100mm2.

 

However, the law of diminishing returns applies since the capacitance and inductance values cannot be reduced to nothing! In other words, pushing the frequency higher will not continually reduce the overall size since there is a limitation to appropriately sized mass produced inductors and capacitors.

 

Transient Response
The transient response is a good indicator of the performance level of a power supply. A Bode plot of each power supply was taken to show a comparison at higher switching frequencies. As shown in Figure 3, the phase margin of each power supply is between 45 and 55 degrees, indicating a well-dampened transient response.

 


 Figure 3: Bode plots at 350 kHz, 700 kHz, and 1600 kHz.

 

The cross over frequency is approximately one-eighth of the switching frequency. When using a fast switching DC/DC converter, make sure the power IC error amplifier has enough bandwidth to support a high crossover frequency. The TPS54317 error amplifier unity gain bandwidth is typically 5MHz. The actual transient response times are shown in Table 4 with the associated voltage peak overshoot value.

 


Table 4: Transient response.

 

The overshoot value is significantly lower with the higher switching frequency, due to the wider bandwidth. Lower transient voltage overshoots are desirable with newer performance processors as their regulation accuracy requirement may be three percent including transient voltage peaks.

When higher output currents are needed, Texas Instruments offers the TPS40140 stackable, dual-channel, 1 MHz DC/DC controller using external MOSFETs. The benefits of a fast switching frequency can be realized by interleaving a number of power stages and switching them out of phase.

 

For example, four outputs can be tied together switching at 500 kHz each, for an effective frequency of 2 MHz. The benefits are lower ripple, reduced input bulk capacitance, faster transient response, and better thermal management by spreading out the power dissipation over the circuit board. Up to eight TPS40140 devices can be connected and synchronized out of phase via digital bus for a maximum effective frequency of 16 MHz.

 

Summary
There are tradeoffs to designing high-frequency switching converters. Some of the advantages shown in this article are a smaller size, faster transient response and smaller voltage over and undershoots. On the other hand, the main penalty paid is a reduction of efficiency and increased heat dissipation.

 

There are potential pitfalls to pushing the envelope such as pulse skipping and noise issues. When selecting a DC/DC converter for high frequency applications, check the manufacturer’s datasheet for important specifications such as the minimum on-time, the gain-bandwidth of the error amplifier, the FET resistance and switching loss. Integrated circuits that perform well in these specifications will cost a premium, but will be worth the price and much easier to use when cornered with a tough design problem.

 

 

選擇DC/DC 轉(zhuǎn)換器最佳開(kāi)關(guān)頻率
作者: 德州儀器Richard Nowakowski 及Brian King

提高開(kāi)關(guān)頻率的好處很明顯,但也有些缺點(diǎn),設(shè)計(jì)人員應(yīng)了解其中的得失利弊,才能選擇最合適的開(kāi)關(guān)頻率來(lái)加以應(yīng)用。這篇實(shí)用文章將逐一說(shuō)明這些考慮因素。

開(kāi)關(guān)頻率很高的直流電源轉(zhuǎn)換器(DC/DC) 正逐漸流行,因?yàn)樗鼈兛梢越逵奢^小的輸出電容和電感,進(jìn)而節(jié)省電路板面積。但另一方面,負(fù)載點(diǎn)電源的需求量卻隨著處理器核心電壓降到1V 以下而變得更嚴(yán)苛,這使得電源供應(yīng)受到負(fù)載周期減少的影響,很難在頻率更高的情形下達(dá)到所要求的更低電壓。

許多電源組件供貨商正在大力推銷(xiāo)速度更快的直流電源轉(zhuǎn)換器,并且宣稱(chēng)他們的產(chǎn)品可以節(jié)省空間。一個(gè)以1 或2MHz 速率切換的直流電源轉(zhuǎn)換器聽(tīng)起來(lái)很棒,但設(shè)計(jì)人員除了關(guān)心體積與效率外,還應(yīng)該了解其它會(huì)對(duì)電源供應(yīng)系統(tǒng)帶來(lái)沖擊的因素。本文將提供幾個(gè)設(shè)計(jì)范例,說(shuō)明提高開(kāi)關(guān)頻率的各種優(yōu)缺點(diǎn)。

選擇應(yīng)用
為了說(shuō)明高開(kāi)關(guān)頻率的得失利弊,本文設(shè)計(jì)和實(shí)作了三種不同的電源供應(yīng),它們的輸入電壓都是5V,輸出電壓是1.8V,而輸出電流則為3A,這些都是DSP、ASIC 或FPGA 等高效能處理器常見(jiàn)的電源要求。在濾波器設(shè)計(jì)和效能的限制下,這些設(shè)計(jì)最多允許20mV 漣波電壓,大約等于輸出電壓的1%,峰對(duì)峰的電感電流則設(shè)為1A。

本文中將會(huì)比較350、700 和1600kHz 等不同頻率的設(shè)計(jì),藉以說(shuō)明它們的優(yōu)缺點(diǎn)。這些范例都以德州儀器(TI) 的TPS54317 做為穩(wěn)壓器,它是一款內(nèi)建MOSFET 的1.6MHz、低電壓、3A 同步直流降壓轉(zhuǎn)換器,具有可程序頻率和外部補(bǔ)償電路,專(zhuān)用于高密度處理器電源負(fù)載點(diǎn)應(yīng)用。

選擇電感與電容
電感與電容都是依據(jù)下列簡(jiǎn)單的公式來(lái)選擇:

公式1:
V = L × di/dt
整理后可得:
L ≧ Vout × (1-D) / (Δ I × Fs)
其中Δ I = 1A 峰對(duì)峰值;D = 1.8V/5V = 0.36。

公式2:
I = C × dv/dt
整理后可得:
C ≧ 2 × Δ I / (8 × Fs × Δ V)
其中:Δ V = 20 mV﹐I = 1A 峰對(duì)峰值。

方程式2 假設(shè)電容的串聯(lián)阻抗可忽略,如陶瓷電容,所以本文中的三個(gè)設(shè)計(jì)都選擇使用阻抗和體積都很小的陶瓷電容。在重新整理后的公式2 中,乘數(shù)2 代表直流偏壓造成的電容值下降,這是因?yàn)槎鄶?shù)陶瓷電容的資料表都未將此效應(yīng)列入考慮。

本文利用圖1 中的電路評(píng)估三種設(shè)計(jì)分別的效能。

圖1:TPS54317 參考電路圖

圖1 里有些組件未標(biāo)示數(shù)值,那是因?yàn)檫@些組件在三種設(shè)計(jì)里的數(shù)值都不相同。輸出濾波器由L1 和C2 組成,它們?cè)谌N設(shè)計(jì)里的數(shù)值分別如表1 所列,這些數(shù)值都是根據(jù)前面的公式計(jì)算而得。

表1:頻率為350kHz、700kHz 和1600kHz 時(shí)所選擇的電容值和電感值

注意頻率越高,電感所需的圈數(shù)就越少,所以直流阻抗就越低。這些誤差放大器的補(bǔ)償零件都是針對(duì)本文中的三種開(kāi)關(guān)頻率所設(shè)計(jì),但這里不會(huì)討論如何計(jì)算及選擇這些組件值。

最小導(dǎo)通時(shí)間
數(shù)字化直流電源轉(zhuǎn)換器所能控制的最小導(dǎo)通時(shí)間,是由脈沖寬度調(diào)變(PWM) 電路所能產(chǎn)生的最小脈沖寬度決定。在降壓轉(zhuǎn)換器里,F(xiàn)ET 導(dǎo)通時(shí)間在整個(gè)開(kāi)關(guān)周期所占的比例稱(chēng)為負(fù)載周期(duty cycle),它等于輸出電壓與輸入電壓的比值。

例如在圖1 電路里,TPS54317 的負(fù)載周期從數(shù)據(jù)表可發(fā)現(xiàn)為0.36 (1.8V/5.0V),最小導(dǎo)通時(shí)間則為150ns (最大值)。設(shè)計(jì)人員只要根據(jù)組件所能控制的最小脈沖寬度,就能利用公式3 輕易算出電路所能達(dá)到的最小負(fù)載周期,再利用公式4 計(jì)算轉(zhuǎn)換器所能提供的最低輸出電壓(參考表2)。值得注意的是,轉(zhuǎn)換器的最低輸出電壓也會(huì)受到參考電壓的限制,例如TPS54317 的參考電壓就是0.9V。

公式3
最小負(fù)載周期= 最小導(dǎo)通時(shí)間× 開(kāi)關(guān)頻率(3)
公式4
最小輸出電壓= 輸入電壓× 最小負(fù)載周期(不得低于TPS54317 的參考電壓) (4)



表2:最小導(dǎo)通時(shí)間為150ns 時(shí)的最小輸出電壓

在此例中,1.6MHz 開(kāi)關(guān)頻率的最小輸出電壓限制為1.2V (譯注:原文此處誤為1.8V)。但若頻率升至3MHz,最小輸出電壓限制就會(huì)增到2.3V。如果直流電源轉(zhuǎn)換器要提供更低的輸出電壓,就必須省略部份脈沖、降低輸入電壓或減少開(kāi)關(guān)頻率。設(shè)計(jì)人員在選擇直流電源轉(zhuǎn)換器的開(kāi)關(guān)頻率前,最好先查詢(xún)數(shù)據(jù)表,確保組件所能控制的最小導(dǎo)通時(shí)間符合設(shè)計(jì)要求。

省略脈沖
若轉(zhuǎn)換器停止閘極驅(qū)動(dòng)脈沖的速度不夠快,無(wú)法達(dá)到所要求的負(fù)載周期,轉(zhuǎn)換器便會(huì)省略部份脈沖(Pulse Skipping) 以提供所需的低輸出電壓。此時(shí),盡管電源供應(yīng)仍會(huì)努力保持輸出電壓穩(wěn)定,但漣波電壓仍會(huì)因?yàn)槊}沖間隔變大而升高。由于省略脈沖的關(guān)系,輸出漣波會(huì)出現(xiàn)某些次諧波成份,這可能會(huì)帶來(lái)噪聲的問(wèn)題。限流電路也可能無(wú)法正常操作,因?yàn)榻M件或許不會(huì)對(duì)大電流突波做出響應(yīng)。有時(shí)甚至控制器都不能正常工作,致使控制回路變得不穩(wěn)定。最快可控制導(dǎo)通時(shí)間是直流電源轉(zhuǎn)換器的一項(xiàng)重要參數(shù),設(shè)計(jì)人員應(yīng)檢查組件數(shù)據(jù)表所列的規(guī)格,確保開(kāi)關(guān)頻率和最小導(dǎo)通時(shí)間都符合要求。

效率與功耗
直流電源轉(zhuǎn)換器的效率是電源供應(yīng)設(shè)計(jì)最重要的考慮因素之一。低效率等于高耗電,需要在電路板上安裝散熱片或擴(kuò)大銅箔面積才能排除熱量。另外,高耗電也會(huì)對(duì)上游電源造成很大的負(fù)擔(dān)。功耗來(lái)源有下列幾種:

影響因素 ·功耗來(lái)源
閘極電荷、驅(qū)動(dòng)電壓和頻率的函數(shù) ·FET 驅(qū)動(dòng)功耗
輸入電壓、輸出電流、FET ·FET 開(kāi)關(guān)功耗 升起/下降時(shí)間以及頻率的函數(shù)
I2 × 導(dǎo)通阻抗 ·FET 阻抗
I2 × 直流阻抗+ 交流核心功耗 ·電感功耗
IRMS2 ·電容功耗 × 等效串聯(lián)組抗
查詢(xún)數(shù)據(jù)表,找出組件操作時(shí)的Iq ·組件功耗(Iq)

在這三個(gè)例子里,主要功耗來(lái)源包括FET 驅(qū)動(dòng)功耗、FET 開(kāi)關(guān)功耗和電感功耗。FET 阻抗與組件功耗則沒(méi)有區(qū)別,因?yàn)檫@三個(gè)設(shè)計(jì)使用同一個(gè)組件。電容功耗也可以忽略,因?yàn)樗鼈兌际褂玫刃Т?lián)阻抗很小的陶瓷電容。為了展示高頻開(kāi)關(guān)的影響,圖2 繪出了這些設(shè)計(jì)測(cè)量而得的效率值。

圖2:不同頻率下提供5V 輸入和1.8V 輸出時(shí)的效率

圖2 清楚顯示開(kāi)關(guān)頻率升高時(shí),效率會(huì)下降。設(shè)計(jì)人員若要改善各種頻率下的效率,就應(yīng)選擇低導(dǎo)通阻抗、低閘極電壓和滿(mǎn)負(fù)載時(shí)靜態(tài)電流很小的直流電源轉(zhuǎn)換器,或者使用等效阻抗更小的電感和電容。

組件尺寸
表3 是電感值和電容值以及它們?cè)陔娐钒迳纤璧暮副P(pán)面積(pad area)。

表3:組件尺寸和總面積需求

電容和電感的建議焊盤(pán)面積都略大于個(gè)別組件,但這點(diǎn)也已列入三個(gè)電路的設(shè)計(jì)考慮。接著只要將個(gè)別零件的使用面積加在一起(包括IC、濾波器和其它小型電阻及電容的焊盤(pán)面積),然后乘以2 以便容納組件間距,就能得到所需的總面積。從表2 可以看出當(dāng)頻率從350kHz 增加到1600kHz 時(shí),濾波器大小會(huì)減少一半,電路板面積則縮小三成,因此所能節(jié)省的面積大約為100 平方毫米。

然而這種做法卻有其限制,因?yàn)殡姼信c電容不可能縮小為零,空間節(jié)省效率也要遵守報(bào)酬遞減法則。換言之,由于大量生產(chǎn)的電感與電容都有尺寸限制,想藉由提高頻率來(lái)縮小總面積的做法不可能無(wú)限延續(xù)下去。

瞬時(shí)響應(yīng)
瞬時(shí)響應(yīng)是很好的電源供應(yīng)效能指標(biāo)。本文繪出了三個(gè)電源供應(yīng)的波德圖(Bode Plot),以便比較它們?cè)谳^高頻率時(shí)的效能。從圖3 可看出這些電源供應(yīng)的相位邊限都在45 到55 度之間,顯示它們都提供良好阻尼的瞬時(shí)響應(yīng)。

圖3:頻率為350kHz、700kHz 和1600kHz 時(shí)的玻德圖(Bode Plot)

交越頻率(cross over frequency) 約為開(kāi)關(guān)頻率的1/8,故使用高開(kāi)關(guān)頻率的直流電源轉(zhuǎn)換器時(shí),應(yīng)確認(rèn)功率組件誤差放大器的頻寬足以支持高交越頻率,例如TPS54317 的誤差放大器增益頻寬典型值就為5MHz。表4 是實(shí)際瞬時(shí)響應(yīng)時(shí)間和相關(guān)的電壓峰overshoot值。

表4:瞬時(shí)響應(yīng)

從表4 中可看出開(kāi)關(guān)頻率越高的設(shè)計(jì),其overshoot 值會(huì)大幅下降,原因是這些設(shè)計(jì)的頻寬會(huì)變得更大。較小的瞬時(shí)電壓overshoot 對(duì)新型高效能處理器比較有利,因?yàn)樗鼈兺ǔR蟀矔r(shí)電壓峰值在內(nèi)的穩(wěn)壓精確度必須達(dá)到3%。

設(shè)計(jì)若需要更大的輸出電流,TI 也提供可多相并聯(lián)、雙通道、1MHz 和使用外接MOSFET的直流電源轉(zhuǎn)換控制器TPS40140。設(shè)計(jì)人員只要將多個(gè)功率級(jí)電路并聯(lián),再讓它們以不同的相位操作,就能將高開(kāi)關(guān)頻率的優(yōu)點(diǎn)帶到應(yīng)用設(shè)計(jì)。

舉例來(lái)說(shuō),設(shè)計(jì)人員可將4 組500kHz 開(kāi)關(guān)頻率的輸出接在一起,以便得到2MHz 的有效頻率。這種做法的好處是能減少漣波、縮小輸入電流容量、加快瞬時(shí)響應(yīng)、和將功耗分散到整張電路板以提供更好的散熱管理。設(shè)計(jì)人員最多能透過(guò)數(shù)字總線把8 個(gè)TPS40140組件連接在一起,并以不同的相位同步操作,使得有效頻率高達(dá)16MHz。

結(jié)語(yǔ)
高開(kāi)關(guān)頻率的交換式電源轉(zhuǎn)換器有利也有弊,本文提到的好處包括體積更小、瞬時(shí)響應(yīng)更快以及電壓overshoot 和undershoot 值都更小,主要缺點(diǎn)則是效率降低和熱量增加。

提高開(kāi)關(guān)頻率還會(huì)帶來(lái)一些潛在問(wèn)題,例如省略脈沖(pulse skipping) 和噪聲,因此在為高頻應(yīng)用選擇直流電源轉(zhuǎn)換器時(shí),應(yīng)先檢查制造商的數(shù)據(jù)表以確認(rèn)某些重要規(guī)格,例如最小導(dǎo)通時(shí)間、誤差放大器增益頻寬、FET 阻抗和開(kāi)關(guān)功耗。在這些規(guī)格上表現(xiàn)良好的組件或許成本會(huì)很高,但它們卻能帶來(lái)更多的好處,遇到設(shè)計(jì)難題時(shí)也更容易使用。

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