元件聲明與元件例化（COMPONENT,PORT MAP）
//或門
LIBRARY IEEE; ；
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2a IS
PORT(a,b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END or2a;
ARCHITECTURE art1 OF or2a IS
BEGIN
c<=a OR b;
END art1;
//半加器；
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT(a,b : IN STD_LOGIC;
co,so: OUT STD_LOGIC);
END h_adder;
ARCHITECTURE art2 OF h_adder IS
BEGIN
so <= a XOR b;
co <= a AND b;
END art2;
1位二進制全加器頂層設(shè)計：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164。ALL;
ENTITY f_adder IS
PORT(ain,bin,cin : IN STD_LOGIC;
cout,sum : OUT STD_LOGIC);
END f_adder;
ARCHITECTURE art3 OF f_adder IS
COMPONENT h_adder //元件聲明；
PORT(a,b : IN STD_LOGIC;
co,so: OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2a
PORT(a,b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END COMPONENT;
SIGNAL d,e,f : STD_LOGIC;
BEGIN
u1:h_adder PORT MAP(ain,bin,d,e); //元件例化；
u2:h_adder PORT MAP(a=>e,b=>cin,co=>f,so=>sum);
u3:or2a PORT MAP(d,f,cout);
END art3;
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