六十進制分秒計數(shù)器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNAL.ALL;
ENTITY clock60 IS
PORT(clk,clr : IN STD_LOGIC;
s1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s10 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
co : OUT STD_LOGIC);
END clock60;
ARCHITECTURE art OF clock60 IS
SIGNAL s1_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s10_temp : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(clk,clr)
BEGIN
IF(clr='1')THEN
s1_temp <= "0000";
s10_temp <= "000";
ELSIF(clk'EVENT AND clk='1')THEN
IF(s1=9)THEN
s1_temp <="0000";
IF(s10_temp=5)THEN
s10_temp="000";
ELSE
s10_temp <= s10_temp+1;
END IF;
ELSE
s1_temp <= s1_temp+1;
END IF;
END IF;
END PROCESS;
s1 <= s1_temp;
s10 <= s10_temp;
co <= '1' WHEN(s10_temp=5 AND s1_temp=9) ELSE
'0';
END art;
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